深圳市尚想信息技术有限公司

IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly Problem: The IO_SMI bit in SMRAM’s location 7FA4h is set to “1” by the processor to indicate that a System Management Interrupt (SMI) occurred as the result of executing an instruction that reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by: • An SMI that is pending while a lower priority event is executing • A REP I/O read • A I/O read that redirects to MWAIT Implication: SMM handlers may get a false IO_SMI indication. Workaround:The SMM handler has to evaluate the saved context to determine if the SMI was triggered by an instruction that read from an I/O port. The SMM handler must not restart an I/O instruction if the platform has not been configured to generate a synchronous SMI for the recorded I/O port address. Status: No Fix. BI2. Writes to IA32_DEBUGCTL MSR May Fail When FREEZE_LBRS_ON_PMI Set Problem: When the FREEZE_LBRS_ON_PMI, IA32_DEBUGCTL MSR (1D9h) bit [11], is set, future writes to the IA32_DEBUGCTL MSR may not occur in certain rare corner cases. Writes to this register by software or during certain processor operations are affected. Implication: Under certain circumstances, the IA32_DEBUGCTL MSR value may not be updated properly and will retain the old value. Intel has not observed this erratum with any commercially available software. Workaround:Do not set the FREEZE_LBRS_ON_PMI bit of IA32_DEBUGCTL MSR. Status: No Fix.