深圳市尚想信息技术有限公司

The TPS382x family of supervisors provide circuit initialization and timing supervision. Optional configurations include devices with active-high and active-low output signals (TPS3824/5), devices with a watchdog timer (TPS3820/3/4/8), and devices with manual reset (MR) pins (TPS3820/3/5/8). RESET asserts when the supply voltage, VDD, rises above 1.1 V. For devices with active-low output logic, the device monitors VDD and keeps RESET low as long as VDD remains below the negative threshold voltage, VIT−. For devices with active-high output logic, RESET remains high as long as VDD remains below VIT−. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td , starts after VDD rises above the positive threshold voltage (VIT− + VHYS). When the supply voltage drops below VIT−, the output becomes active (low) again. All the devices of this family have a fixed-sense threshold voltage, VIT– , set by an internal voltage divider, so no external components are required.